Abstract:

Electronic systems increasingly demand a new class of semiconductor technologies that simultaneously deliver energy efficiency, sustainability, scalability, and manufacturability under stringent thermal and integration constraints. Oxide semiconductors offer a compelling platform to meet these needs, combining low-temperature processability and compatibility with large-area and three-dimensional (3D) integration.

In this talk, I will present my research on advancing oxide semiconductor transistors for next-generation electronic and nanosystem applications. I will begin by outlining the current landscape and fundamental challenges of oxide semiconductor devices, with a particular emphasis on the long-standing bottleneck of high-performance p-channel oxide transistors for CMOS circuits. I will then highlight my recent work on p-type oxide transistors, demonstrating performance enhancements enabled by material design and defect-termination strategies.

Beyond p-type oxides, I will introduce my research on low-temperature-processed ultrawide-bandgap (UWBG) semiconductor thin-film electronics, which establishes an emerging materials and device platform for sensing and on-chip power electronics. To enable high-density 3D integrated circuits, I will examine device scaling in oxide semiconductor transistors. Finally, I will share my recent efforts in collaborating with semiconductor foundries to enable the lab-to-fab translation of oxide semiconductors and devices, bridging fundamental research with industrial implementation.

Biography:

Chi-Hsin Huang is a postdoctoral scholar in the Department of Electrical Engineering at Stanford University, working under the guidance of Prof. H.-S. Philip Wong since June 2024. He is a recipient of the 2024 Taiwan Science and Technology Hub at Stanford Postdoctoral Fellowship. He earned his Ph.D. in Electrical and Computer Engineering from the University of California, San Diego, under the supervision of Prof. Kenji Nomura. Prior to that, he received his B.S. in Chemical Engineering from National Cheng Kung University and an M.S. in Materials Science and Engineering from National Tsing Hua University. From 2013 to 2017, he worked as an engineer at Taiwan Semiconductor Manufacturing Company (TSMC), where he developed thin-film processes for advanced CMOS technology (16nm, 10 nm, 7 nm, 5nm). In the summer of 2022, he interned at Applied Materials, investigating the device architecture and process integration of 3D-stacked complementary field-effect transistors (CFETs) for next-generation CMOS technology nodes beyond 2nm. His research focuses on the design and development of oxide semiconductors and devices for future electronic applications.